Inverse-designed acoustic splitters

Inverse design · MATLAB–COMSOL

Simulated acoustic field passing through a scattering region — Simulated acoustic field for a scattering pattern, from slide 27 of my August 2024 qualification presentation.

Inverse design in photonics

Inverse-designed integrated photonic devices with irregular, non-intuitive patterns — Inverse-designed integrated photonic devices. From Nat. Photonics 9, 374 (2015) and Nat. Photonics 9, 378 (2015).

In conventional design, a designer picks a structure and simulates what it does. Inverse design reverses the process: you specify what the device should do, and an algorithm searches for a structure that does it. In integrated photonics, this approach has produced ultra-compact wavelength and mode demultiplexers with irregular, non-intuitive patterns that a person would be unlikely to draw.

An inverse-designed acoustic power splitter

Simulated acoustic field through a random scattering pattern with one input and two outputs, the circular scattering unit, and the 20 by 20 design region in 200 nm AlN — The splitter concept: a 20 × 20 design region of scattering units (holes of diameter d in cells of size a) in 200 nm AlN, between a 1 µm input waveguide and two outputs.

I asked whether the same idea works for gigahertz acoustic waves: can a patterned scattering region split acoustic power between two outputs in a chosen ratio? The design region is a 20 × 20 grid of scattering units in a 200 nm AlN film. Each unit is either a hole or no hole, and the hole diameter d and cell size a are additional parameters. An input waveguide feeds the region, and two output waveguides collect the power.

I built the design workflow in MATLAB and COMSOL: MATLAB coordinates the design loop, and COMSOL models the acoustic response of each candidate geometry.

COMSOL setup showing the port excitation, the perfectly matched layer selection and the refined mesh in the scattering region — COMSOL setup: port excitation (0.01 W, A0 mode at 1 GHz), perfectly matched layers (PMLs) at the outputs, and a finer mesh with 3–4 boundary layers in the scattering region.

In a first round, I simulated candidate patterns with an A0-mode input at 1 GHz and 10 mW, with PMLs absorbing the power at each output. I measured the power reaching each output against a target split ratio of 9 : 1.

First-round results

Simulated displacement fields for four scattering patterns, with the power at each output and S11 — Simulated displacement magnitude for four scattering patterns, with the power absorbed at each output PML and S11.

Simulation results from qualification slide 28 (August 2024). Input: 10 mW; target output ratio: 9 : 1. Ratios are calculated from the rounded powers.
Case	a (nm)	d (nm)	Output 1 (mW)	Output 2 (mW)	Ratio	S11
1	150	120	4.3	1.0	4.3 : 1	0.093
2	250	220	5.7	1.0	5.7 : 1	0.014
3	400	320	4.9	0.9	5.4 : 1	0.0385
4	400	320	6.4	1.1	5.8 : 1	0.0852

Cases 3 and 4 use the same a and d with different hole patterns. None of these first-round patterns reached the 9 : 1 target; the best gave about 5.8 : 1. The summed output power was also well below the 10 mW input, so a real optimizer needs to target both the ratio and the transmission. This round established the simulation pipeline and the parameter ranges for a proper optimization loop.

Device layout for fabrication

Full mask layout with IDTs in etching windows, tapered couplers and the scattering unit, with a zoom on the metalized or etched holes — Full mask layout: IDTs in etching windows, tapered couplers, and the scattering unit, with a zoom on the metalized/etched holes.

To test a design experimentally, the simulated scattering region must be embedded in a complete device. The full layout includes:

IDTs inside etching windows to launch and detect the wave;
tapered couplers to funnel it into the 1 µm waveguide;
the scattering region itself, realized either as etched or as metalized holes.

I wrote Python tools to convert the design geometry into multilayer CAD masks automatically, so a new candidate pattern can go straight from simulation to fabrication layout.

Project status — August 2024

The simulation pipeline and the fabrication layout were in place. Next steps were device fabrication, reducing computation time so that a full optimization loop is practical, and testing the splitter with electrical and TMIM measurements. All results above are simulations, not measurements of a completed splitter.